1. Field of the Invention
The present invention generally relates to the art of microelectronic precision current switch arrays for digital-to-analog converters (DAC) and other applications, and more specifically to a current switch array including bias current compensation for individual transistor current gain and thermally induced base-emitter voltage drop variation.
2. Description of the Related Art
A digital-to-analog converter (DAC) is used for converting a digital signal consisting of a number of digital binary bits into a continuously variable voltage or current. DACs per se are known in the art such as described in a textbook entitled "BIPOLAR AND MOS ANALOG INTEGRATED CIRCUIT DESIGN", by Alan B. Grebene, John Wiley & Sons, 1984, Chapter 14 entitled "DATA CONVERSION CIRCUITS: DIGITAL-TO-ANALOG CONVERSION", pp. 753-824.
DACs can use either voltage or current scaling. A typical DAC 10 which uses current scaling and produces a differential voltage output in response to a single-ended voltage input is illustrated in FIG. 1. The DAC 10 includes a plurality of transistor data current switches S1 to SN, where N is the number of bits of the digital binary word to be converted to analog form. The individual bits are input to the switches S1 to SN as digital bit inputs DATA1 to DATAN, which turn the switches S1 to SN on or off depending on the logical sense of the respective digital input.
The outputs of the switches S1 to SN are connected to a resistor scaling ladder network 12 including series resistors RS and parallel resistors RP in an arrangement which is symmetrical about ground to produce differential analog voltage outputs VOUT+ and VOUT-. The resistors RS and RP are designed to scale the outputs of the switches S1 to SN depending on the binary weights of the respective bits.
A reference voltage generator or source 14 generates a positive reference voltage VREF which is applied through a resistor R1 to a current source IS0 to cause a bias current IBIAS to flow through the source IS0. The source IS0 produces a variable bias voltage VBREF which is automatically adjusted by the source IS0 to maintain the bias current IBIAS equal to a predetermined value.
The bias voltage VBREF is applied to current sources IS1 to ISN which cause bias currents which are equal or proportional to the bias current IBIAS to flow through the switches S1 to SN respectively. When one or more of the switches S1 to SN are closed in accordance with the value of the digital input, current flows from ground through the associated resistors in the network 12, the closed switches S1 to SN and the current sources IS1 to ISN respectively to a negative D.C. voltage source VEE.
The currents through the switches S1 to SN are scaled and summed by the network 12 to produce the differential analog output voltages VOUT+ and VOUT-. An operational or other differential amplifier 16 may be provided to produce a single-ended analog output voltage VOUT which is proportional to the difference between the differential output voltages VOUT+ and VOUT- and thereby to the value of the digital input signal represented by the bit inputs DATA1 to DATAN.
An example of the current sources IS0 and IS1 and the switch S1 as illustrated on page 793 of the above referenced textbook to Grebene is illustrated in FIG. 2. The reference voltage VREF from the source 14 is applied through the resistor R1 to the non-inverting input of an operational amplifier 18 which is connected in a negative feedback configuration. The inverting input of the amplifier 18 is connected to ground.
The output of the amplifier 18 is connected to the base of an NPN bipolar transistor Q1, the emitter of which is connected through a resistor R2 to the source VEE. The collector of the transistor Q1 is connected to the non-inverting input of the amplifier 18.
The amplifier 18 produces the bias voltage VBREF at its output, and adjusts the value of VBREF and thereby the base voltage and current flow through the transistor Q1 until the voltage at the non-inverting input of the amplifier 18 is equal to the voltage at the inverting input thereof. Since the inverting input of the amplifier 18 is grounded, the voltage VBREF will be adjusted to maintain the voltage at the non-inverting input of the amplifier 18 at zero volts.
This causes the voltage VREF to be dropped across the resistor R1 such that the current IBIAS through the resistor R1 is equal to VREF divided by the resistance value of the resistor R1. Since substantially no current can flow through the non-inverting input of the amplifier 18, the current IBIAS is forced to flow into the collector of the transistor Q1.
The switch S1 includes NPN transistors Q2 and Q3 which are connected in a differential configuration with their emitters connected together. The collectors of the transistors Q2 and Q3 produce differential current outputs IOUT+ and IOUT- which are applied to the scaling network 12. The digital input DATA1 is applied to the base of the transistor Q2, whereas a bias voltage VBIAS is applied to the base of the transistor Q3.
The emitters of the transistors Q2 and Q3 are connected through a regulating transistor Q4 of the source IS1. The emitter of the transistor Q4 is connected through a resistor R3 to the source VEE, whereas the bias voltage VBREF is applied to the base of the transistor Q4.
The transistor Q3 provides a switching threshold at the voltage VBIAS which is preferably equal to one-half the maximum value of the input DATA1. When the input DATA1 is high, the transistor Q2 is turned on and the transistor Q3 is turned off, and vice-versa. The transistor Q4 is biased by the voltage VBREF to cause a constant bias current which is proportional to the current IBIAS to flow through the emitter of whichever of the transistors Q2 and Q3 is turned on.
Assuming that the transistors Q1 and Q4 and the resistors R2 and R3 are identical, the collector current of the transistor Q4 which constitutes the bias current for the transistors Q2 and Q3 will be equal to IBIAS.
However, since the transistors Q2 and Q3 have finite base current, the output current IOUT+ or IOUT- will be smaller than IBIAS by the base current of the transistor Q2 or Q3 respectively. In addition, the base currents of the transistors Q2 and Q3 will vary depending on the deviation in the actual current gain .beta. of the transistors Q2 and Q3 from their predetermined design current gain, and temperature induced variations in emitter-base voltage and base current.
To cancel these variations, the direct connection between the collector of the transistor Q1 and the non-inverting input of the amplifier 18 is replaced by an NPN transistor Q5 as illustrated in broken line. The collector of the transistor Q5 is connected to the non-inverting input of the amplifier 18, whereas the emitter of the transistor Q5 is connected to the collector of the transistor Q1. The voltage VBIAS is applied to the base of the transistor Q5.
The transistor Q5 is designed to be identical to the transistors Q2 and Q3, such that the base currents of the transistors Q2 and Q3 will be the same as the base current I5 of the transistor Q5 at a particular value of bias voltage VBIAS. Thus, a base current I5 of the transistor Q5 is added to IBIAS in the feedback loop around the amplifier 18, and the bias voltage VBREF is adjusted to regulate the collector current of the transistor Q1 and thereby Q4 to IBIAS+I5.
The collector current of whichever transistor Q2 or Q3 is turned on is equal to the emitter current minus the base current thereof, with the base current being equal to I5. The collector current of the transistor Q2 or Q3 is therefore equal to IBIAS.
The switches S2 to SN and the current sources IS2 to ISN are identical to the switch S1 and current source IS1. The addition of the transistor Q5 provides global compensation for base current variations of the transistors in the switches S1 to SN in that the bias voltage VBREF is compensated by the transistor Q5 to be proportional to absolute temperature (PTAT), and is fanned out to all of the current sources IS1 to ISN respectively.
However, a practical DAC includes a large number, for example 64, current switches fabricated as a monolithic integrated circuit on a single chip. Due to the limitations of practical microcircuit fabrication technology, the current gain .beta. of the transistors will not be identical as desired. The tolerance between adjacent transistors is typically several percent, and this tolerance spread out as a gradient across a chip such that the .beta. of transistors at opposite ends of a chip can differ by over ten percent.
This causes the currents representing the individual bits of the digital input to vary from their design values, and cause distortion which limits the linearity and accuracy of the analog output signal.
In addition, the base-emitter voltage drops Vbe of the current source transistors vary as a function of temperature. More specifically, Vbe decreases as temperature increases. This causes an increase in emitter current for a given value of base voltage. There can be a substantial temperature gradient across a large integrated circuit chip, which will cause the Vbe of the individual transistors to vary from each other and cause distortion and non-linearity.
The transistor Q5 in the prior art arrangement of FIG. 2 is therefore able to provide only global or first order compensation for variations in bias current, and is incapable of compensating for differences between individual transistors and temperature variations across a large chip.